Some MarkIII? Mux Notes
These are notes that I've developed over the past year or so in a text file, mostly for myself, that may provide some useful context for new, or less hardware oriented, people in the project. There is some overlap to text descriptions Rick Shafer has provided elsewhere on the wiki, and many missing details.
Each bolometer can be considered as a variable resistor. For the Penn
Array our bolometers are voltage biased, and the 64 detectors are
grouped into 8 logical columns (note that a logical column is not what
you would think of as a geometrical column-- as it turns out, a
logical column is a half of of a quadrant geometrically). Each the
current flow through each bolometer induces a magnetic flux through
the first stage squid (SQ1), which in turn changes the resistance of
the squid in a periodic fashion. SQ1, like all SQUIDs in the SMUX,
has two key controllable parameters: a bias voltage and a magnetic
flux offset (aka "offset" or "feedback"). For SQ1 the bias voltage is
controlled by the address driver, a component which is inside the
dewar and connected to the focal plane via flexline. The address
driver cycles through all rows in a specifiable sequence, setting the
bias for the selected row to a predetermined level, and setting the
bias for all other rows to zero. In effect this "activates" only one
row of SQ1's (one SQ1 in a column) at a time. The magnetic flux
offset is servo'd automatically by warm digital electronics in order
to maintain the SQUID near its point of maximum responsivity and
linearity (since SQUIDs have sinusoidal V-Phi_B curves). The magnetic
flux offset at any given point in time is in principal proportional to
the current flowing throw the bolometer up to an arbitrary offset; in
turn, the current flowing through the bolometer is proportional to
incident radiation power. The flux offset servo loop is closed at 50
MHz and the warm electronics pass the total flux offset back to the
computer via the PCI card as a 14 bit value (the "DAC" value, ie, the
commanded voltage that generates the flux offset). There is also a 16
bit "ERROR" signal indicating the difference in the commanded flux
offset and the readout flux offset for that sample (i.e., the
difference in the "ADC lock point" and the actual ADC value which has
been read). Up to an arbitrary gain, the ERROR signal can be summed
to give the same information as the 14 bit total flux offset;
depending on the value of the gain between the DAC and ADC channels,
one may provide greater dynamic range.
Each SQ1 in a column is in turn inductively coupled to a summing
circuit comprising a bunch of inductors in series; this summing
circuit is coupled to the second stage squid amplifier (SQ2). Note
that each column will also have a "dark" SQUID which is not coupled to
a detector on this summing circuit (the dark squid is not shown in
many diagrams, and should not be confused with the stage 2 squid). The
dark squid will be used to remove drifts in the electronics. As
explained previously only one SQ1 in a column is active at a time, so
although all of the SQ1 outputs are coupled in series, only one is
seen at SQ2 instantaneously. The second stage bias and offset are set
by programmable voltage outputs of bias cards in the analog
electronics tower; these parameters must tuned by hand or some other
procedure, and are not automatically configured or servo'd in any
fashion by the MUX system electronics.
The SQ2 output is routed to a final stage of amplification, the
"series array" or "SA" (aka SQ3) , which consists of a series of
SQUIDs in series, inductively coupled to the SQ2 output. Like the 2nd
stage SQUIDs, the bias level and feedback are set by bias cards in the
analog tower. The output of the series array is routed to the preamp
card in the analog tower, and from there to the warm electroncs
(specifically, the signal for this column is routed to a Digital
Feedback Card [DFB] dedicated to this column). The preamp card in the
analog tower also has a programmable voltage output used to bias the
SA. The SA offset is set by one of the outputs in a bias card.
Since the SQUID biases and feedbacks are key parameters from an
operator's point of view, it's worth recapping who controls the bias
and the feedback for each stage of the SQUID Multiplexer:
Bias FB
SQ1 Address Driver DFB
SQ2 Bias Card Bias Card
SQ3 Preamp Card Bias Card
=SA
he Address Driver is cold, and located within the dewar; the bias
cards and preamp cards are warm, and located on top of the dewar; and
the Digital Feedack Card is located in the electronics rack.
The specific paramaters which, in the nominal instrument configuration
(ie no recabling as in the lab squid tuning tests), control the squid
biases and feedbacks listed above are enumerated below. In
parentheses the number of these parameters for the penn array is
listed; in square brackets the interface software is indicated.
PARAMETER COUNT
SQ1 Bias Level (N=1 parameter??) --> set via [address board/addresscontrol] in "adc hi"
I think but am not sure the address line bias levels are common for the whole
system (at least for the penn array, where the whole system runs through
a single address card in the tower)
SQ1 Feedback -- has numerous parameters: (ADC offset, DAC offset, P, I) x Ndetectors = 256 parameters
[these are all set in "DFB Mux Control", where you select the desired DFB card (column)
in the "send address" window]
SQ2 Bias Level (N=Ncolumns=8) [set the "DAC level" in "tower control" at the appropriate card address]
SQ2 Feedback (N=Ncolumns=8) [ditto]
SQ3 (series Array) bias level (N=Ncolumns=8) [ditto]
SQ3 Feedback (N=Ncolumns=8) [ditto]
Figure 5 of the Reintsema paper usefully summarizes the MUX DAQ timing
scheme. Briefly consider a single column. A single detector (ie one
row of that column) is dwelled upon for a number of master clock
pulses set by the parameter LSYNC. Two things happen in parallel
during this time. First the bias (address) line which controls the
1st stage SQUID in question waits for DELAY clock pulses and then
comes on, activating the SQUID, for a duration specified by WIDTH.
Simultaneously, the ADC which samples the output waits for SETTLE
pulses, and then samples NSAMP times.
The process in the preceeding parallel happens in parallel for each
column, with each column being controlled by one DFB card.
The parameters which control the timing, and how you set them, are:
-LSYNC=duration of one row readout [set in "Mux Clock", under "line period"
tab, "line period" window]
-DELAY=S1 bias delay, ie, duration of low voltage state [set in "Address Board", delay tab, delay box]
-WIDTH=duration of S1 high voltage state bias [set in "Address Board", width tab, width box]
-SETTLE=ADC blanking period [set in "DFB Mux Control", "Number of Samples" box]
-NSAMP= number of ADC samples on one row [set in "DFB Mux Control", "Number of Samples" box]
These are all measured in units of the 50 MHz master clock.
Constraints on the parameters are:
DELAY+WIDTH=LSYNC-1 ??
SETTLE+NSAMP=LSYNC-1??
*detector: 1.. Ndet
--> ea has (el, xel) offsets. calib params (G, ...)
--> in principle, each detector could be live or dark: is this a (limit of?) calibration param.
*muxCh: 1.. Nrow x Ncol.
--> ea can be a detector OR a dark channel. calib params.
sensor row, sensor column coord.
*DFB card
--> card address, [slot number], sensor column, NIST channel.
*each sensor column has: {Bias, FB} for {SQ2, SA} -- four
voltages. each voltage has a tower card address and a channel number.
MUX=Multiplexer
SMUX=SQUID Multiplexer, equals, in practical terms, MUX.
S1=SQ1= 1st stage Squid (etc for 2). Note that the "3rd stage squid"
is the series array
SA=series array
FB=feed back (loosely aka "offset" or "magnetic flux offset", "flux offset")
DFB=digital feedback card
PID=proportional/integral feedback algorithm (Princeton usually chooses P=I so it's
just an integral feedback)
DEB=digital elextronics box (warm rack containing DFB cards, clock card, and other muxing stuff)
ADC=analog to digital converter; usually refers to the thing that actually samples the data
DAC=digital to analog converter=programmable power supply, used to bias various stages of
the system properly. Note that the DFB also has a DAC which is what closes the feedback
loop on the first stage squids.
very rough... Rick's spec is much more detailed and physical.
NOTE: the "observable" quantity in the folowing procedure (ie what you
read back) is the error signal. This assumes that the DFB DAC (except
in the very last step, where we use function generator mode) is
sending a constant output.
1)Tune series array ("third stage squid")
-sweep into SA FB
--at each setting, read out the error signal. build up a curve this way
--vary bias until the curve looks right
--> remember bias, FB
--> do this procedure Ncolumns times, possibly in parallel.
2)Tune second stage squid
-sweep into SQ2 FB
--at each setting, read out the error signal. build up a curve this way
-tweak SQ2 bias
-tweak SA FB to get rid of weird offsets & wrapping, if needed
--> remember bias, FB
--> do this procedure Ncolumns times, possibly in parallel
3)Tune first stage squid
-sweep into SQ1 FB (ie put DFB into function generator mode)
-at each setting, read out the error signal. build up a curve this way
-vary row address current
-vary SQ2 FB if needed
-vary SA FB if needed
--> remember bias (row address current), FB (this will be useful in
locking up the MUX)
--> I think you do this Ncolumns x Nrows times. However the row address
current only has Nrows values and thus crosses columns. SQ1FB has
Ncolumns x Nrows values.
Optical Fiber Connections. Here I assume cards are mounted in the crate and you are looking at the connection ports in the back.
- The top (blue) input accepts commands from the computer on the serial link (serial to fiber converter on back of PC)
- The 2nd to top (grey) output of the clock card goes to CLK input on the back of the PCI card
- The bottom connector on the DFB sends data to PCI data channels (connections inside the computer chassis)
- the top connector of one of the DFB cards goes to the Frame synch connection on the back of the PCI card.
Rick Shafer's IrcMarkIIITerminology wiki page is useful.
-- BrianMason - 02 Feb 2005
Revision r1.3 - 11 Jul 2007 - 17:18 GMT - BrianMason
Parents: WebHome > MarkIIITopLevel > MarkIIISystem
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